Subject: General Tech | August 30, 2011 - 12:34 PM | Jeremy Hellstrom
Tagged: tape out, GLOBALFOUNDRIES, amd, 20nm
When then discussion turns to a chip taping out, we are referring to an obsolete practice where a chip would be designed on a large scale and then reduced through photolithography. Originally, once a chip design was finalized on paper it went to the artwork stage where an engineer would literally tape out and glue the design to create a photomask which would allow light through in a variety of ways or utterly block it. That light was focused to create a smaller version, which then was used to make an even smaller version ... until it was of a size to etch the physical components of the chip onto the wafer and with a bit of luck and a lot of skill you would end up with a chip that worked to the specs you expected.
You can't exactly do that anymore, as the current generation of chips coming out of GLOBALFOUNDRIES uses a 20nm process, smaller than even extreme UV wavelengths and the magnitude of size reduction would be insurmountable. Thankfully there is CAD and many other more mature ways of creating chips than the old cut and paste method. This puts AMD in a good position to transfer to a 20nm process in the future, smaller than Intel's 22nm process but lacking the Tri-Gate three dimensional transistors that Intel will be implementing. Drop by The Inquirer for more.
"CHIPSHOP Globalfoundaries has announced that it taped out a test chip using its 20nm process node.
Globalfoundaries, best known for being the main chip fab partner of AMD, has been working to get its 28nm and 20nm process nodes up and running. For Globalfoundaries and its customers - in particular, AMD - having a mature 20nm process is desirable to show it has possibilities for die-shrinkage in the near future."
Here is some more Tech News from around the web:
- New USB 3.0 Flash Drive Has 2 TB of Storage @ Slashdot
- Windows 8 Explorer will support native mounting of ISO and VHD @ ExtremeTech
- Microsoft shows off Windows 8 ribbon interface @ The Inquirer
- Ultrabooks may push down mainstream notebook prices @ DigiTimes
- Fraudulent Google credential found in the wild @ The Register
- Wacom Intuos4 Medium Professional Pen Tablet Review @ Real World Labs
- Sony Cyber-shot DSC-HX100V Review @ TechReviewSource
- Celebrating 30 Years of the PC @ TechSpot
Subject: Shows and Expos | August 11, 2011 - 06:30 PM | Jeremy Hellstrom
Tagged: GLOBALFOUNDRIES, GTC 2011
Milpitas, Calif. – August 11, 2011 – GLOBALFOUNDRIES today announced the agenda for its second annual Global Technology Conference (GTC) on Tuesday, August 30 at the Santa Clara Convention Center in Santa Clara, Calif. GTC 2011 will be a seminal opportunity to learn about the vision and strategy of the new GLOBALFOUNDRIES leadership team, in addition to featuring executives and technologists from throughout the semiconductor ecosystem.
“In the past two months, I have spent a great deal of time working with and listening to our customers,” said Ajit Manocha, chief executive officer of GLOBALFOUNDRIES. “They are critical to our success, and we are committed to delivering the innovation and technology solutions that they are demanding from the foundry industry. We are excited to take this opportunity to update our customers, partners and the rest of the ecosystem on the business momentum we’ve achieved since GTC 2010 and particularly over the last few months.”
GTC 2011 will feature a keynote address by Manocha and presentations from other members of the GLOBALFOUNDRIES executive leadership as well as management and technical teams. The conference also will include a highlight from the previous year’s event—a panel discussion among senior executives in the EDA/IP ecosystem examining industry trends and challenges in leading-edge design enablement. Moderated by Mojy Chian, GLOBALFOUNDRIES senior vice president of design enablement, the panel will feature the following participants:
- Warren East, chief executive officer, ARM
- Lip-Bu Tan, president and chief executive officer, Cadence Design Systems
- Aart de Geus, chairman of the board and chief executive officer, Synopsys
- Robert Hum, vice president and general manager, Deep Submicron Division, Mentor Graphics
“At last year’s inaugural GTC event, we received a tremendous response from the industry as we outlined our plans to change the foundry landscape and revive competition at the leading edge,” said Jim Kupec, senior vice president of sales and marketing at GLOBALFOUNDRIES. “We have made a great deal of progress and overcome significant challenges to become the only foundry in volume production of leading-edge High-k Metal Gate (HKMG) technology. We look forward to sharing our successes and demonstrating our continued commitment to bringing a differentiated model to the foundry industry.”
In addition, GLOBALFOUNDRIES will present “Leading in Innovation” awards to customers and partners who are working with the company on products ranging from 0.35um non-volatile to 130nm and 65nm RFCMOS, and leading-edge 28nm technologies for processors and high-speed, low-power analog solutions. These awards epitomize the GTC 2011 theme of driving product innovation through true collaboration between GLOBALFOUNDRIES and its ecosystem partners on leading edge and mainstream CMOS technologies, as well as solutions for high voltage, embedded non-volatile memories, RF, analog, and MEMS.
GTC 2011 is expected to draw more than 1,500 people from around the world, including broad participation from key customers, suppliers, partners, industry analysts and media as well as the GLOBALFOUNDRIES leadership team. The Santa Clara event will kick off a series of GTC 2011 “Road Show” events to be held at other strategic international venues including:
- September 14, Hsinchu, Taiwan
- September 16, Shanghai, China
- October 27, Tokyo, Japan
Each regional event features members of the GLOBALSOLUTIONSTM ecosystem of partners exhibiting proven, differentiated solutions in design enablement, mask services, assembly and test for the consumer, communications, computing and automotive sectors.
Please visit the following Web site for details on the agenda, keynotes, exhibitions, demos and other features of the event: http://www.globalfoundries.com/gtc2011/.
Subject: General Tech | July 12, 2011 - 11:15 AM | Jeremy Hellstrom
Tagged: new york, GLOBALFOUNDRIES, fab 8, fab 1, dresden, cleanroom
Milpitas, Calif. – July 12, 2011 – Just over one year after revealing plans for a major global capacity expansion, GLOBALFOUNDRIES today announced its newly constructed cleanrooms in New York and Dresden are ready for the installation of 300mm semiconductor wafer fabrication equipment. Achieving “Ready for Equipment” (RFE) status marks the transition from the construction phase to the operations phase—a significant milestone on the path to volume manufacturing in these new facilities.
“At GLOBALFOUNDRIES, we continue to invest aggressively in driving sustained growth on advanced technologies,” said GLOBALFOUNDRIES CEO Ajit Manocha. “The build-out of our 300mm manufacturing campuses in New York and Dresden is supporting growing customer demand for advanced technologies, while creating hundreds of jobs and providing a significant boost to the economies in the surrounding regions. By completing these massive construction projects on schedule and on budget, we are continuing to deliver on our commitment to being the only truly global foundry.”
At Fab 1 in Dresden, Germany, GLOBALFOUNDRIES has completed construction of an additional wafer manufacturing facility designed to add capacity at 45nm and below, which has the potential to increase the overall output of the Fab 1 campus to 80,000 wafers per month once fully ramped. The expansion project will add more than 110,000 square feet of cleanroom space to the site and will allow Fab 1 to operate as one integrated cleanroom. This extension will make Dresden the largest wafer fab in Europe for leading-edge technology.
At Fab 8, GLOBALFOUNDRIES’ newest semiconductor manufacturing facility under construction at the Luther Forest Technology Campus in Saratoga County, New York, the RFE date was moved up by nearly two months to meet heavy customer demands. Last week, GLOBALFOUNDRIES moved into the facility’s Admin 1 office building and broke ground on the Admin 2 building. Once completed, Fab 8 will stand as the most technologically advanced wafer fab in the world and the largest leading-edge semiconductor foundry in the United States. When fully built-out and ramped, the total available cleanroom space will be approximately 300,000 square feet and will be capable of a total output of approximately 60,000 wafers per month. The total facility, including cleanroom support infrastructure and office space, includes approximately 1.9 million square feet of space and is expected to come online in 2012 with volume production targeted for early 2013. Fab 8 will focus on leading-edge manufacturing at 28nm and below.