Subject: General Tech | September 16, 2014 - 11:38 AM | Jeremy Hellstrom
Tagged: FinFET, flexible
We've seen a few examples of OLEDs being used to create flexible displays but they are much slower than their unbending silicon rivals. With conductive ink and thread it is possible to make wearable technology but again the silicon components remain solid and immobile. Researchers in Saudi Arabia have been working on flexible technology which retains the speed of silicon transistors but is able to flex up to 0.5 mm which may sound large until you remember the size of a transistor. They have created these FinFETs by putting a thin layer of a polymer on top of the material they will be etching the transistors into and gently removing the polymer once the process has completed. This results in a FinFET which retains the power saving and performance attributes common to the 3D transistor but with the ability to bend. This won't be marketed for a while yet but in the mean time read all about it on Nanotechweb.
"Researchers at the King Abdullah University of Science and Technology in Saudia Arabia are continuing with their experiments to transform traditional rigid electronic wafers made from silicon into mechanically flexible and transparent ones."
Here is some more Tech News from around the web:
- Tunnelling electrons make new type of transistor @ Nanotechweb
- IBM brings Watson Analytics to all with freemium model @ The Inquirer
- Seagate's triple-headed Cerberus could SAVE the DISK WORLD @ The Register
- Amazon Kindle vulnerability lets hackers take over your account @ The Inquirer
- be quiet! Straight Power 10 competition @ Kitguru
Coming in 2014: Intel Core M
The era of Broadwell begins in late 2014 and based on what Intel has disclosed to us today, the processor architecture appears to be impressive in nearly every aspect. Coming off the success of the Haswell design in 2013 built on 22nm, the Broadwell-Y architecture will not only be the first to market with a new microarchitecture, but will be the flagship product on Intel’s new 14nm tri-gate process technology.
The Intel Core M processor, as Broadwell-Y has been dubbed, includes impressive technological improvements over previous low power Intel processors that result in lower power, thinner form factors, and longer battery life designs. Broadwell-Y will stretch into even lower TDPs enabling 9mm or small fanless designs that maintain current battery lifespans. A new 2nd generation FIVR with modified power delivery design allows for even thinner packaging and a wider range of dynamic frequencies than before. And of course, along with the shift comes an updated converged core design and improved graphics performance.
All of these changes are in service to what Intel claims is a re-invention of the notebook. Compared to 2010 when the company introduced the original Intel Core processor, thus redirecting Intel’s direction almost completely, Intel Core M and the Broadwell-Y changes will allow for some dramatic platform changes.
Notebook thickness will go from 26mm (~1.02 inches) down to a small as 7mm (~0.27 inches) as Intel has proven with its Llama Mountain reference platform. Reductions in total thermal dissipation of 4x while improving core performance by 2x and graphics performance by 7x are something no other company has been able to do over the same time span. And in the end, one of the most important features for the consumer, is getting double the useful battery life with a smaller (and lighter) battery required for it.
But these kinds of advancements just don’t happen by chance – ask any other semiconductor company that is either trying to keep ahead of or catch up to Intel. It takes countless engineers and endless hours to build a platform like this. Today Intel is sharing some key details on how it was able to make this jump including the move to a 14nm FinFET / tri-gate transistor technology and impressive packaging and core design changes to the Broadwell architecture.
Intel 14nm Technology Advancement
Intel consistently creates and builds the most impressive manufacturing and production processes in the world and it has helped it maintain a market leadership over rivals in the CPU space. It is also one of the key tenants that Intel hopes will help them deliver on the world of mobile including tablets and smartphones. At the 22nm node Intel was the first offer 3D transistors, what they called tri-gate and others refer to as FinFET. By focusing on power consumption rather than top level performance Intel was able to build the Haswell design (as well as Silvermont for the Atom line) with impressive performance and power scaling, allowing thinner and less power hungry designs than with previous generations. Some enthusiasts might think that Intel has done this at the expense of high performance components, and there is some truth to that. But Intel believes that by committing to this space it builds the best future for the company.
The Really Good Times are Over
We really do not realize how good we had it. Sure, we could apply that to budget surpluses and the time before the rise of global terrorism, but in this case I am talking about the predictable advancement of graphics due to both design expertise and improvements in process technology. Moore’s law has been exceptionally kind to graphics. We can look back and when we plot the course of these graphics companies, they have actually outstripped Moore in terms of transistor density from generation to generation. Most of this is due to better tools and the expertise gained in what is still a fairly new endeavor as compared to CPUs (the first true 3D accelerators were released in the 1993/94 timeframe).
The complexity of a modern 3D chip is truly mind-boggling. To get a good idea of where we came from, we must look back at the first generations of products that we could actually purchase. The original 3Dfx Voodoo Graphics was comprised of a raster chip and a texture chip, each contained approximately 1 million transistors (give or take) and were made on a then available .5 micron process (we shall call it 500 nm from here on out to give a sense of perspective with modern process technology). The chips were clocked between 47 and 50 MHz (though often could be clocked up to 57 MHz by going into the init file and putting in “SET SST_GRXCLK=57”… btw, SST stood for Sellers/Smith/Tarolli, the founders of 3Dfx). This revolutionary graphics card at the time could push out 47 to 50 megapixels and had 4 MB of VRAM and was released in the beginning of 1996.
My first 3D graphics card was the Orchid Righteous 3D. Voodoo Graphics was really the first successful consumer 3D graphics card. Yes, there were others before it, but Voodoo Graphics had the largest impact of them all.
In 1998 3Dfx released the Voodoo 2, and it was a significant jump in complexity from the original. These chips were fabricated on a 350 nm process. There were three chips to each card, one of which was the raster chip and the other two were texture chips. At the top end of the product stack was the 12 MB cards. The raster chip had 4 MB of VRAM available to it while each texture chip had 4 MB of VRAM for texture storage. Not only did this product double performance from the Voodoo Graphics, it was able to run in single card configurations at 800x600 (as compared to the max 640x480 of the Voodoo Graphics). This is the same time as when NVIDIA started to become a very aggressive competitor with the Riva TnT and ATI was about to ship the Rage 128.
Taking a Fresh Look at GLOBALFOUNDRIES
It has been a while since we last talked about GLOBALFOUNDRIES, and it is high time to do so. So why the long wait between updates? Well, I think the long and short of it is a lack of execution from their stated roadmaps from around 2009 on. When GF first came on the scene they had a very aggressive roadmap about where their process technology will be and how it will be implemented. I believe that GF first mentioned a working 28 nm process in a early 2011 timeframe. There was a lot of excitement in some corners as people expected next generation GPUs to be available around then using that process node.
Fab 1 is the facility where all 32 nm SOI and most 28 nm HKMG are produced.
Obviously GF did not get that particular process up and running as expected. In fact, they had some real issues getting 32 nm SOI running in a timely manner. Llano was the first product GF produced on that particular node, as well as plenty of test wafers of Bulldozer parts. Both were delayed from when they were initially expected to hit, and both had fabrication issues. Time and money can fix most things when it comes to process technology, and eventually GF was able to solve what issues they had on their end. 32 nm SOI/HKMG is producing like gangbusters. AMD has improved their designs on their end to make things a bit easier as well at GF.
While shoring up the 32 nm process was of extreme importance to GF, it seemingly took resources away from further developing 28 nm and below processes. While work was still being done on these products, the roadmap was far too aggressive for what they were able to accomplish. The hits just kept coming though. AMD cut back on 32nm orders, which had a financial impact on both companies. It was cheaper for AMD to renegotiate the contract and take a penalty rather than order chips that it simply could not sell. GF then had lots of line space open on 32 nm SOI (Dresden) that could not be filled. AMD then voided another contract in which they suffered a larger penalty by opting to potentially utilize a second source for 28 nm HKMG production of their CPUs and APUs. AMD obviously was very uncomfortable about where GF was with their 28 nm process.
During all of this time GF was working to get their Luther Forest FAB 8 up and running. Building a new FAB is no small task. This is a multi-billion dollar endeavor and any new FAB design will have complications. Happily for GF, the development of this FAB has gone along seemingly according to plan. The FAB has achieved every major milestone in construction and deployment. Still, the risks involved with a FAB that could reach around $8 billion+ are immense.
2012 was not exactly the year that GF expected, or hoped for. It was tough on them and their partners. They also had more expenses such as acquiring Chartered back in 2009 and then acquiring the rather significant stake that AMD had in the company in the first place. During this time ATIC has been pumping money into GF to keep it afloat as well as its aspirations at being a major player in the fabrication industry.
Subject: General Tech | April 2, 2013 - 02:57 PM | Jeremy Hellstrom
Tagged: arm, FinFET, 16nm, TSMC, Cortex-A57
While what DigiTimes is reporting on is only the first tape out, it is still very interesting to see TSMC hitting 16nm process testing and doing it with the 3D transistor technology we have come to know as FinFET. It was a 64-bit ARM Cortex-A57 chip that was created using this process, unfortunately we did not get much information about what comprised the chip apart from the slide you can see below.
As it can be inferred by the mention that it can run alongside big.LITTLE chips it will not be of the same architecture, nor will it be confined to cellphones. This does help reinforce TSMC's position in the market for keeping up with the latest fabrication trends and another solid ARM contract will also keep the beancounters occupied. You can't expect to see these chips immediately but this is a solid step towards an new process being mastered by TSMC.
"The achievement is the first milestone in the collaboration between ARM and TSMC to jointly optimize the 64-bit ARMv8 processor series on TSMC FinFET process technologies, the companies said. The pair has teamed up to produce Cortex-A57 processors and libraries to support early customer implementations on 16nm FinFET for ARM-based SoCs."
Here is some more Tech News from around the web:
- Wiping a Smartphone Still Leaves Data Behind @ Slashdot
- ARM processor competition to fire up @ DigiTimes
- Physicists bang the drum for quantum memory @ The Register
- Intel Haswell Socket H Heatsink Requirements and Overclocking Thoughts @ Tweaktown
- Killing Your Internet with Killer Ethernet @ Techgage
- Backdoors Found In Bitlocker, FileVault and TrueCrypt? @ TechARP
- Win ASRock FM2A85X Extreme 6 & Seasonic M12II-850 @ Kitguru
- Win Enermax Goodies From Insomnia i48 @ eTeknix
- NikKTech & Synology Joint Giveaway - One DiskStation DS213+ Up For Grabs
- The TR Podcast 131: News from GDC and FCAT attacks
- Dispatches from the Nexus @ The Tech Report
- AMD touts unified gaming strategy @ The Tech Report
- Intel gets serious about graphics for gaming @ The Tech Report
Subject: Editorial | January 16, 2013 - 06:41 PM | Josh Walrath
Tagged: ST Ericsson, planar, PD-SOI, L8580, FinFET, FD-SOI, Cortex A9, cortex a15, arm
SOI has been around for some time now, but in partially depleted form (PD-SOI). Quite a few manufacturers have utilized PD-SOI for their products, such as AMD and IBM (probably the two largest producers of SOI based parts). Oddly enough, Intel has shunned SOI wafers altogether. One would expect Intel to spare no expense to have the fastest semiconductor based chips on the market, but SOI did not provide enough advantages for the chip behemoth to outweigh the nearly 10% increase in wafer and production costs. There were certainly quite a few interesting properties to PD-SOI, but Intel was able to find ways around bulk silicon’s limitations. These non-SOI improvements include stress and strain, low-K dialectrics, high-K metal gates, and now 3D FinFET Technology. Intel simply did not need SOI to achieve the performance they were looking for while still using bulk silicon wafers.
Things started looking a bit grim for SOI as a technology a few years back. AMD was starting to back out of utilizing SOI for sub-32 nm products, and IBM was slowly shifting away from producing chips based on their Power technology. PD-SOI’s days seemed numbered. And they are. That is ok though, as the technology will see a massive uptake with the introduction of Fully Depleted SOI wafers. I will not go into the technology in full right now, but expect another article further into the future. I mentioned in a tweet some days ago that in manufacturing, materials are still king. This looks to hold true with FD-SOI.
Intel had to utilize 3D FinFETs on 22 nm because they simply could not get the performance out of bulk silicon and planar structures. There are advantages and disadvantages to these structures. The advantage is that better power characteristics can be attained without using exotic materials all the while keeping bins high, but the disadvantage is the increased complexity of wafer production with such structures. It is arguable that the increase in complexity completely offsets the price premium of a SOI based solution. We have also seen with the Intel process that while power consumption is decreased as compared to the previous 32 nm process, the switching performance vs. power consumption is certainly not optimal. Hence the reason why we have not seen Intel release Ivy Bridge parts that are clocked significantly faster than last generation Sandy Bridge chips.
FD-SOI and planar structures at 22 nm and 20 nm promise the improve power characteristics as compared to bulk/FinFET. It also looks to improve overall power vs. clockspeed as compared to bulk/FinFET. In a nutshell this means better power consumption as well as a jump in clockspeed as compared to previous generations. Gate first designs using FD-SOI could be very good, but industry analysts say that gate last designs could be “spectacular”.
So what does this have to do with ST Ericsson? They are one of the first companies to show a products based on 28 nm FD-SOI technology. The ARM based NovaThore L8580 is a dual Cortex A9 design with the graphics portion being the IMG SGX544. At first glance we would think that ST is behind the ball, as other manufacturers are releasing Cortex A15 parts which improve IPC by a significant amount. Then we start digging into the details.
The fastest Cortex A9 designs that we have seen so far have been clocked around 1.5 GHz. The L8580 can be clocked up to 2.5 GHz. Whatever IPC improvements we see with A15 are soon washed away by the sheer clockspeed advantage that the L8580 has. While it has been rumored that the Tegra 4 will be clocked up to 2 GHz in tablet form, ST is able to get the L8580 to 2.5 GHz in a smartphone. NVIDIA utilizes a 5th core to improve low power performance, but ST was able to get their chip to run at 0.6v in low power mode. This decrease in complexity combined with what appears to be outstanding electrical and thermal characteristics makes this a very interesting device.
The Cortex A9 cores are not the only ones to see an improvement in clockspeed and power consumption. The well known and extensively used SGX544 graphics portion runs at 600 MHz in a handheld device, and is around 20% faster clocked than other comparable parts.
When we add all these things together we have a product that appears to be head and shoulders above current parts from Qualcomm and Samsung. It also appears that these parts are comparable, if not slightly ahead, of the announced next generation of parts from the Cortex A15 crowd. It stands to reason that ST Ericsson will run away with the market and be included in every new handheld sold from now until the first 22/20 nm parts are released? Unfortunately for ST Ericsson, this is not the case. If there was an Achilles Heel to the L8580 it is that of production capabilities. ST Ericsson started production on FD-SOI wafers this past spring, but it was processing hundreds of wafers a month vs. the thousands that are required for full scale production. We can assume that ST Ericsson has improved this situation, but they are not exactly a powerhouse when it comes to manufacturing prowess. They simply do not seem to have the FD-SOI production capabilities to handle orders from more than a handful of cellphone and table manufacturers.
ST Ericsson has a very interesting part, and it certainly looks to prove the capabilities of FD-SOI when compared to competing products being produced on bulk silicon. The Nova Thor L8580 will gain some new customers with its combination of performance and power characteristics, even though it is using the “older” Cortex A9 design. FD-SOI has certainly caught the industrys’ attention. There are more FD-SOI factoids floating around that I want to cover soon, but these will have to wait. For the time being ST Ericsson is on the cutting edge when it comes to SOI and their proof of concept L8580 seems to have exceeded expectations.
Subject: General Tech | September 21, 2012 - 10:58 AM | Jeremy Hellstrom
Tagged: 14nm, FinFET, 3d transistors, GLOBALFOUNDRIES, SoC
Intel was first out of the gate with their 3D transistors, which they dubbed Tri-gate and which the rest of the world refers to as FinFET as the normal 2D transistor is flipped on its side in a position reminiscent of a fin. This leads to much more efficient power usage, perfect for mobile designs and needed as the transistor density at 14nm is going to be quite high. GLOFO's 14nm eXtreme Mobility will work in conjunction with the current 20nm process used to fabricate SOCs and will be the basis of many lines of chips, such as ARM who have signed a multiyear contract with GLOFO. Check out DigiTimes for more.
"Globalfoundries has announced the launch of a new technology designed for the expanding mobile market. The new 14nm-XM offering will give customers the performance and power benefits of three-dimensional "FinFET" transistors with less risk and a faster time-to-market, helping the fabless ecosystem maintain its leadership in mobility while enabling a new generation of smart mobile devices, according to the foundry."
Here is some more Tech News from around the web:
- Microsoft releases VMware-EATER @ The Register
- Deep, deep dive inside Intel's next-generation processor @ The Register
- Oh, Sublime Text, how do I love thee @ The Tech Report
- NVIDIA To Publicly Release Some Documentation @ Phoronix
- Logitech C920 HD Pro Webcam Review @ NikKTech (As seen on the PCPer Podcast)
- How to repair a ribbon cable connection on consumer electronics @ Hack a Day
- Apple iOS 6 Review @ TechReviewSource
- Win AFOX HD7850 Single Slot Crossfire @ Kitguru
Subject: General Tech | March 16, 2012 - 09:16 AM | Jeremy Hellstrom
Tagged: tri-gate, FinFET, silicon nanowires
We've just met Intel's Tri-Gate transistor technology, which offers significant improvements in power efficiency as well as reducing waste hear but researchers have already moved onto the next new technology. Referred to as silicon nanowire transistors in this story at The Register, the next generation of transistor may have no gates whatsoever, or be made entirely of gates, depending on how you look at it. The wire will be wrapped in a silicon oxide, high-K metal gate making the transistor cylindrical and not limited in the number of gates possible in the same way that planar or 3D transistors are. The development of this technology is in its infancy but could well help us see chips go below 5nm as it matures.
"The next step in transistor architecture will likely be silicon nanowires – extremely thin silicon wires that will form the transistor's chanel, surrounded on all sides by a wrap-around silicon oxide, high-K metal gate.
"It's the ultimate fully-depleted device," the director of IBM's Semiconductor Research & Development Center, Gary Patton, said during his keynote address at Wednesday's Common Platform Technology Forum 2012 in Santa Clara, California. "You don't have a gate on just two sides, or three sides – it's fully encapsulating the silicon nanowire device."
Here is some more Tech News from around the web:
- Thunderbolt may become standard for PCs in 2013 @ DigiTimes
- WD releases Thunderbolt drive @ The Register
- Sophos warns about fresh Windows exploit @ The Inquirer
- I bought a Kindle Touch, and it's pretty great @ The Tech Report
- Scosche reVOLT c2 Dual USB Car Charger Review @ Legit Reviews
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