Subject: Storage | August 12, 2013 - 09:00 AM | Allyn Malventano
Tagged: ssd, silicon motion, sata, controller
You may very well have never heard of Silicon Motion (SMI), a major priducer of flash memory controllers, even if you've followed the SSD industry for a while. This is primarily because the vast majority of their products have been tailored for the devices that folks tend to not crack open during review, namely USB memory sticks, eMMC devices, and SD / CF cards:
Creating controllers in those arenas will tend to force a company to do a few things very well:
- Handle a very limited number of flash channels with the greatest speed possible, due to packaging requirements for very small devices.
- Operate at the lowest power draw possible as to meet the current draw limits of the host interface.
This has resulted in SMI developing a 6Gb/sec SSD controller, dubbed the SM2246EN, using the above techniques:
The block diagram shows what appears to be a fairly standard 4-channel configuration, though there are fewer steps in the pipeline as compared to SandForce and other controllers, which should help decrease latency and improve efficiency. There is also no compression engine, which means power consumption should be further reduced.
Read on for further details on specs and power consumption, followed by the full press blast.
Marvell, a storage technology company founded in 1995, today announced a new SSD controller in the form of the 88SS9187 that supports many of the latest storage technologies and is set to debut in several products this year.
The new 88SS9187 SSD controller is reportedly powered by a powerful embedded processor and supports the SATA 3.1 (6Gbps) interface as well as a NAND flash interface that is capable of up to 200 MB/s per channel. Also, the Marvell controller can support on-chip RAID functionality as well as Adaptive Read and Write Scheme technology in the ECC (error correction code) engine.
Marvell also claims that the 88SS9187 controller supports the DDR3 DRAM interface for "up to 1 G byte memory," and approximately 500 MB/s of sequential write performance under dirty drive conditions. The claim that the new controller will provide Random read and write IOPS with minimum over provisioning and performance degradations (where provisioning is used to provide a buffer for wear leveling algorithms and extra space for the drive controller to work with to increase performance). The Vice President of Marketing for Marvell's Storage Business Group Alan Armstrong, stated that the new 88SS9187 controller will enable SSD manufacturers "to fully customize their products to meet specific customer demands and distinguish their products based on price, performance, power and functionality."
They plan for the new controller to have an impact in both the consumer and enterprise markets and have announced that additional partners will integrate the 88SS9187 controller into their SSDs later this year. For now though, they have only stated that a "significant number" of popular SSD manufacturers will have drives ready in the immediate future. More information is available here.
Subject: Storage | February 16, 2012 - 09:51 PM | Allyn Malventano
Tagged: Xtensa, VIA, Tensilica, ssd, DPU, controller
VIA has always been known for the 'slow and steady' approach to computing. They might not have the quickest stuff around, but they certainly tend to have the lowest power draw. While we haven't seen many releases from VIA as of late, they appear to be gearing up for a rediscovered purpose for their mantra - Solid State Storage.
VIA has brought on a company called Tensilica, who make a System on a Chip (SoC) architecture that has been purpose built for moving data around. The system, dubbed the Xtensa dataplane processor (DPU), has some particular math strengths that would be very beneficial if applied to the realm of an SSD controller. For example, the DPU is capable of performing multiple simultaneous table lookups within a single clock cycle. This is handy for increasing the IOPS rating of an SSD, since wear leveling and write amplification are handled by remapping the LBA's (sectors) to flash memory space. Each IO results in a necessary table lookup, which the DPU can perform very quickly.
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