Subject: Graphics Cards, Processors, Mobile | June 4, 2015 - 04:58 PM | Scott Michaud
Tagged: amd, carrizo
My discussion of the Carrizo architecture went up a couple of days ago. The post did not include specific SKUs because we did not have those at the time. Now we do, and there will be products: one A8-branded, one A10-branded, and one FX-branded.
All three will be quad-core parts that can range between 12W and 35W designs, although the A8 processor does not have a 35W mode listed in the AMD Dual Graphics table. The FX-8800P is an APU that has all eight GPU cores while the A-series APUs have six. The A10-8700P and the A8-8600P are separated by a couple hundred megahertz base and boost CPU clocks, and 80 MHz GPU clock.
Also, we have been given a table of AMD Radeon R5 and R7 M-series GPUs that can be paired with Carrizo in an AMD Dual Graphics setup. These GPUs are the R7 M365, R7 M360, R7 M350, R7 M340, R5 M335, and R5 M330. They cannot be paired with every Carrizo APU, and some pairings only work in certain power envelopes. Thankfully, this table should only be relevant to OEMs, because end-users are receiving pre-configured systems.
Pricing and availability will depend on OEMs, of course.
Subject: General Tech | June 3, 2015 - 05:29 PM | Jeremy Hellstrom
Tagged: carrizo, APU, amd. excavator
If you skipped reading Scott's look at the new AMD Carrizo processor you have done yourself a disfavour and should read through his look at AMD's recent history and the evolution of Bulldozer and Steamroller into Excavator. It will help you understand The Tech Report's look into the new architecture and the AMD provided benchmarks which you can check out here. A lot of the new architecture is a refinement of previous chips but the Tonga based GPU portion is completely new and looks to be an impressive improvement, especially on these 15W and 30W chips. It will be very interesting to see how they fare against the Iris Pro on Intel's new Broadwell chips in systems without a discrete GPU.
"The Carrizo processor is AMD's follow-on to Kaveri and a direct competitor to Intel's Broadwell CPUs. After a lengthy prelude, AMD is officially taking the wraps off of Carrizo today at the Computex trade show in Taipei. The firm expects laptops based on Carrizo to be available near the end of this month, and now that the chip is official, we know a number of juicy details about it that had previously been murky."
Here is some more Tech News from around the web:
- Typing 'http://:' Into a Skype Message Trashes the Installation Beyond Repair @ Slashdot
- Microsoft suffers worldwide Wi-Fi wardrobe malfunction @ The Register
- Fanbois designing Windows 10 – where's it going to end? @ The Register
- Holy SSH-it! Microsoft promises secure logins for Windows PowerShell @ The Register
- Tech ARP 2015 Mega Giveaway #4 : Mi In-Ear Headphones
Digging into a specific market
A little while ago, I decided to think about processor design as a game. You are given a budget of complexity, which is determined by your process node, power, heat, die size, and so forth, and the objective is to lay out features in the way that suits your goal and workload best. While not the topic of today's post, GPUs are a great example of what I mean. They make the assumption that in a batch of work, nearby tasks are very similar, such as the math behind two neighboring pixels on the screen. This assumption allows GPU manufacturers to save complexity by chaining dozens of cores together into not-quite-independent work groups. The circuit fits the work better, and thus it lets more get done in the same complexity budget.
Carrizo is aiming at a 63 million unit per year market segment.
This article is about Carrizo, though. This is AMD's sixth-generation APU, starting with Llano's release in June 2011. For this launch, Carrizo is targeting the 15W and 35W power envelopes for $400-$700 USD notebook devices. AMD needed to increase efficiency on the same, 28nm process that we have seen in their product stack since Kabini and Temash were released in May of 2013. They tasked their engineers to optimize their APU's design for these constraints, which led to dense architectures and clever features on the same budget of complexity, rather than smaller transistors or a bigger die.
15W was their primary target, and they claim to have exceeded their own expectations.
Backing up for a second. Beep. Beep. Beep. Beep.
When I met with AMD last month, I brought up the Bulldozer architecture with many individuals. I suspected that it was a quite clever design that didn't reach its potential because of external factors. As I started this editorial, processor design is a game and, if you can save complexity by knowing your workload, you can do more with less.
Bulldozer looked like it wanted to take a shortcut by cutting elements that its designers believed would be redundant going forward. First and foremost, two cores share a single floating point (decimal) unit. While you need some floating point capacity, upcoming workloads could use the GPU for a massive increase in performance, which is right there on the same die. As such, the complexity that is dedicated to every second FPU can be cut and used for something else. You can see this trend throughout various elements of the architecture.
Some Fresh Hope for 2016
EDIT 2015-05-07: A day after the AMD analyst meeting we now know that the roadmaps delivered here are not legitimate. While some of the information is likely correct on the roadmaps, they were not leaked by AMD. There is no FM3 socket, rather AMD is going with AM4. AMD will be providing more information throughout this quarter about their roadmaps, but for now take all of this information as "not legit".
SH SOTN has some eagle eyes and spotted the latest leaked roadmap for AMD. These roadmaps cover both mobile and desktop, from 2015 through 2016. There are obviously quite a few interesting tidbits of information here.
On the mobility roadmap we see the upcoming release of Carrizo, which we have been talking about since before CES. This will be the very first HSA 1.0 compliant part to hit the market, and AMD has done some really interesting things with the design in terms of performance, power efficiency, and die size optimizations. Carrizo will span the market from 15 watts to 35 watts TDP. This is a mobile only part, but indications point to it being pretty competent overall. This is a true SOC that will support all traditional I/O functions of older standalone southbridges. Most believe that this part will be manufactured by GLOBALFOUNDIRES on their 28 nm HKMG process that is more tuned to AMD's APU needs.
Carrizo-L will be based on the Puma+ architecture and will go from 10 watts to 15 watts TDP. This will use the same FP4 BGA connection as the big Carrizo APU. This should make these parts more palatable for OEMs as they do not have to differentiate the motherboard infrastructure. Making things easier for OEMs will give more reasons for these folks to offer products based on Carrizo and Carrizo-L APUs. The other big reason will be the GCN graphics compute units. Puma+ is a very solid processor architecture for low power products, but these parts are still limited to the older 28 nm HKMG process from TSMC.
One interesting addition here is that AMD will be introducing their "Amur" APU for the low power and ultra-low power markets. These will be comprised of four Cortex-A57 CPUs combined with AMD's GCN graphics units. This will be the first time we see this combination, and the first time AMD has integrated with ARM since ATI spun off their mobile graphics to Qualcomm under the "Adreno" branding (anagram for "Radeon"). What is most interesting here is that this APU will be a 20 nm part most likely fabricated by TSMC. This is not to say that Samsung or GLOBALFOUNDRIES might be producing it, but those companies are expending their energy on the 14 nm FinFET process that will be their bread and butter for years to come. This will be a welcome addition to the mobile market (tablets and handhelds) and could be a nice profit center for AMD if they are able to release this in a timely manner.
2016 is when things get very interesting. The Zen x86 design will dominate the upper 2/3 of the roadmap. I had talked about Zen when we had some new diagram leaks yesterday, but now we get to see the first potential products based off of this architecture. In mobile it will span from 5 watts to 35 watts TDP. The performance and mainstream offerings will be the "Bristol Ridge" APU which will feature 4 Zen cores (or one Zen module) combined with the next gen GCN architecture. This will be a 14nm part, and the assumption is that it will be GLOBALFOUNDRIES using 14nm FinFET LPP (Low Power Plus) that will be more tuned for larger APUs. This will also be a full SOC.
The next APU will be codenamed "Basilisk" that will span the 5 watt to 15 watt range. It will be comprised of 2 Zen cores (1/2 of a Zen module) and likely feature 2 to 4 MB of L3 cache, depending on power requirements. This looks to be the first Skybridge set of APUs that will share the same infrastructure as the ARM based Amur SOC. FT4 BGA is the basis for both the 2015 Amur and 2016 Basilisk SOCs.
Finally we have the first iteration of AMD's first ground up implementation of ARM's ARMv8-A ISA. The "Styx" APU features the new K12 CPU cores that AMD has designed from scratch. It too will feature the next generation GCN units as well as share the same FT4 BGA connection. Many are anxiously watching this space to see if AMD can build a better mousetrap when it comes to licensing the ARM ISA (as have Qualcomm, NVIDIA, and others).
2015 shows no difference in the performance desktop space, as it is still serviced by the now venerable Piledriver based FX parts on AM3+. The only change we expect to see here is that there will be a handful of new motherboard offerings from the usual suspects that will include the new USB 3.1 functionality derived from a 3rd party controller.
Mainstream and Performance will utilize the upcoming Godavari APUs. These are power and speed optimized APUs that are still based on the current Kaveri design. These look to be a simple refresh/rebadge with a slight performance tweak. Not exciting, but needs to happen for OEMs.
Low power will continue to be addressed by Beema based APUs. These are regular Puma based cores (not Puma+). AMD likely does not have the numbers to justify a new product in this rather small market.
2016 is when things get interesting again. We see the release of the FM3 socket (final proof that AM3+ is dead) that will house the latest Zen based APUs. At the top end we see "Summit Ridge" which will be composed of 8 Zen cores (or 2 Zen modules). This will have 4 MB of L2 cache and 16 MB of L3 cache if our other leaks are correct. These will be manufactured on 14nm FinFET LPE (the more appropriate process product for larger, more performance oriented parts). These will not be SOCs. We can expect these to be the basis of new Opterons as well, but there is obviously no confirmation of that on these particular slides. This will be the first new product in some years from AMD that has the chance to compete with higher end desktop SKUs from Intel.
From there we have the lower power Bristol Ridge and Basilisk APUs that we already covered in the mobile discussion. These look to be significant upgrades from the current Kaveri (and upcoming Godavari) APUs. New graphics cores, new CPU cores, and new SOC implementations where necessary.
AMD will really be shaking up the game in 2016. At the very least they will have proven that they can still change up their game and release higher end (and hopefully competitive) products. AMD has enough revenue and cash on hand to survive through 2016 and 2017 at the rate they are going now. We can only hope that this widescale change will allow AMD to make some significant inroads with OEMs on all levels. Otherwise Intel is free to do what they want and what price they want across multiple markets.
Subject: Processors | April 27, 2015 - 06:06 PM | Josh Walrath
Tagged: Zen, Steamroller, Kaveria, k12, Excavator, carrizo, bulldozer, amd
There are some pretty breathless analysis of a single leaked block diagram that is supposedly from AMD. This is one of the first indications of what the Zen architecture looks like from a CPU core standpoint. The block diagram is very simple, but looks in the same style as what we have seen from AMD. There are some labels, but this is almost a 50,000 foot view of the architecture rather than a slightly clearer 10,000 foot view.
There are a few things we know for sure about Zen. It is a clean sheet design that moves away from what AMD was pursuing with their Bulldozer family of cores. Zen gives up CMT for SMT support for handling more threads. The design has a cluster of four cores sharing 8 MB of L3 cache, with each core having access to 512 KB of L2 cache. There is a lot of optimism that AMD can kick the trend of falling more and more behind Intel every year with this particular design. Jim Keller is viewed very positively due to his work at AMD in the K7 through K8 days, as well as what he accomplished at Apple with their ARM based offerings.
One of the first sites to pick up this diagram wrote quite a bit about what they saw. There was a lot of talk about, “right off the bat just by looking at the block diagram we can tell that Zen will have substantially higher single threaded performance compared to Excavator and the Bulldozer family.” There was the assumption that because it had two 256-bit FMACs that it could fuse them to create a single 512 bit AVX product.
These assumptions are pretty silly. This is a very simple block diagram that answers few very important questions about the architecture. Yes, it shows 6 int pipelines, but we don’t know how many are address generation vs. execution units. We don’t know how wide decode is. We don’t know latency to L2 cache, much less how L3 is connected and shared out. So just because we see more integer pipelines per core does not automatically mean, “Da, more is better, strong like tractor!” We don’t know what improvements or simplifications we will see in the schedulers. There is no mention of the front-end other than Fetch and Decode. How about Branch Prediction? What is the latency for the memory controller when addressing external memory?
Essentially, this looks like a simplified way of expressing to analysts that AMD is attempting to retain their per core integer performance while boosting floating point/AVX at a similar level. Other than that, there is very little that can be gleaned from this simple block diagram.
Other leaks that are interesting concerning Zen are the formats that we will see these products integrated into. One leak detailed a HPC aimed APU that features 16 Zen cores with 32 MB of L3 cache attached to a very large GPU. Another leak detailed a server level chip that will support 32 cores and will be seen in 2P systems. Zen certainly appears to be very flexible, and in ways it reminds me of a much beefier Jaguar type CPU. My gut feeling is that AMD will get closer to Intel than it has been in years, and perhaps they can catch Intel by surprise with a few extra features. The reality of the situation is that AMD is far behind and only now are we seeing pure-play foundries start to get even close to Intel in terms of process technology. AMD is very much at a disadvantage here.
Still, the company needs to release new, competitive products that will refill the company coffers. The previous quarter’s loss has dug into cash reserves, but AMD is still stable in terms of cash on hand and long term debt. 2015 will see new GPUs, an APU refresh, and the release of the new Carrizo parts. 2016 looks to be the make or break year with Zen and K12.
Edit 2015-04-28: Thanks to SH STON we have a new slide that has been leaked from the same deck as this one. This has some interesting info in that AMD may be going away from exclusive cache designs. Exclusive was a good idea when cache was small and expensive, as data was not replicated through each level of cache (L1 was not replicated in L2 and L2 was not replicated in L3). Intel has been using inclusive cache since forever, where data is replicated and simpler to handle. Now it looks like AMD is moving towards inclusive. This is not necessarily a bad thing as the 512 KB of L2 can easily handle what looks to be 128 KB of L1 and the shared 8 MB of L3 cache can easily handle the 2 MB of L2 data. Here is the link to that slide.
The new slide in question.
Subject: General Tech | April 21, 2015 - 03:07 PM | Jeremy Hellstrom
Tagged: tonga, linux, carrizo, AMDGPU, amd
It will not be officially rolled in until kernel 4.2 but you can currently grab the new binary blob by following the links from Phoronix. This new AMDGPU kernel driver will be used by both the full open-source driver and the Catalyst driver provided officially by AMD and provide support not only for the R9 285 but upcoming families as well. There is still some development to be done as AMD's Alex Deucher told Phoronix that this initial code lacks power management features for Tonga but that will be addressed shortly.
"At long last the source code to the new AMDGPU driver has been released! This is the new driver needed to support the Radeon R9 285 graphics card along with future GPUs/APUs like Carrizo. Compared to the existing Radeon DRM driver, the new AMDGPU code is needed for AMD's new unified Linux driver strategy whereby the new Catalyst driver will be isolated to being a user-space binary blob with both the full open-source driver and the Catalyst driver using this common AMDGPU kernel driver."
Here is some more Tech News from around the web:
- Memristor could help make brain-like computer @ Nanotechweb
- Qualcomm will reportedly ditch TSMC in favour of Samsung for Snapdragon 820 @ The Inquirer
- BlackBerry buys security startup WatchDox to boost enterprise software offering @ The Inquirer
- Windows 10 MURDERED your Lumia? Microsoft says it may have a fix @ The Register
- How to Run Your Own Git Server @ Linux.com
- D-Link: sorry we're SOHOpeless @ The Register
- MSI OC Academy Sub-Zero Overclocking Event @ Kitguru
- TRENDnet AC1900 Dual Band Wireless Router Review @ NikKTech
- Inateck HBU3VL2-4 USB 3.0 Hub and HBU3VL3-4 Hub with Ethernet @ eTeknix
Subject: Processors | February 24, 2015 - 06:18 PM | Jeremy Hellstrom
Tagged: Puma+, Puma, Kaveri, ISSCC 2015, ISSCC, GCN, Excavator, Carrizo-L, carrizo, APU, amd
While it is utterly inconceivable that Josh might have missed something in his look at Carrizo, that hasn't stopped certain Canadians from talking about Gila County, Arizona. AMD's upcoming processor launch is a little more interesting than just another Phenom II launch, especially for those worried about power consumption. With Adaptive Voltage and Frequency Scaling the new Excavator based chips will run very well at the sub-15W per core pair range which is perfect for POS, airplane entertainment and even in casinos. The GPU portion speaks to those usage scenarios though you can't expect an R9 295 at that wattage. Check out Hardware Canucks' coverage right here.
"AMD has been working hard on their mobile Carrizo architecture and they're now releasing some details about these Excavator architecture-equipped next generation APUs."
Here are some more Processor articles from around the web:
- AMD's new Carrizo: The x86 notebook processor that thinks it's a GPU @ The Register
- AMD Carrizo APU Details Revealed @ TechARP
- AMD FX-8320E Performance On Linux @ Phoronix
- Intel Broadwell HD Graphics 5500: Windows 8.1 vs. Linux @ Phoronix
- Preliminary Tests Of Intel Sandy Bridge & Ivy Bridge vs. Broadwell @ Phoronix
AMD Details Carrizo Further
Some months back AMD introduced us to their “Carrizo” product. Details were slim, but we learned that this would be another 28 nm part that has improved power efficiency over its predecessor. It would be based on the new “Excavator” core that will be the final implementation of the Bulldozer architecture. The graphics will be based on the latest iteration of the GCN architecture as well. Carrizo would be a true SOC in that it integrates the southbridge controller. The final piece of information that we received was that it would be interchangeable with the Carrizo-L SOC, which is a extremely low power APU based on the Puma+ cores.
A few months later we were invited by AMD to their CES meeting rooms to see early Carrizo samples in action. These products were running a variety of applications very smoothly, but we were not informed of speeds and actual power draw. All that we knew is that Carrizo was working and able to run pretty significant workloads like high quality 4K video playback. Details were yet again very scarce other than the expected timeline of release, the TDP ratings of these future parts, and how it was going to be a significant jump in energy efficiency over the previous Kaveri based APUs.
AMD is presenting more information on Carrizo at the ISSCC 2015 conference. This information dives a little deeper into how AMD has made the APU smaller, more power efficient, and faster overall than the previous 15 watt to 35 watt APUs based on Kaveri. AMD claims that they have a product that will increase power efficiency in a way not ever seen before for the company. This is particularly important considering that Carrizo is still a 28 nm product.
Subject: General Tech | January 22, 2015 - 11:39 AM | Ken Addison
Tagged: podcast, video, asus, Rampage V Extreme, Samsung, T1, 850 EVO, ECS, liva x, amazon echo, amd, carrizo, windows 10, raptr
PC Perspective Podcast #333 - 01/22/2015
Join us this week as we discuss the ASUS Rampage V Extreme, Samsung T1 Portable SSD, Windows 10 and more!
The URL for the podcast is: http://pcper.com/podcast - Share with your friends!
- iTunes - Subscribe to the podcast directly through the Store
- RSS - Subscribe through your regular RSS reader
- MP3 - Direct download link to the MP3 file
Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, and Allyn Malventano
Program length: 1:22:33
Week in Review:
News items of interest:
0:57:45 Intel and AMD 4th quarter earnings
Hardware/Software Picks of the Week:
Ryan: Airbnb - sleep in someone else's bed
Subject: Processors | January 18, 2015 - 05:16 PM | Sebastian Peak
Tagged: SoC, rumor, processor, leak, iris pro, Intel, graphics, cpu, carrizo, APU, amd
A new report of leaked benchmarks paints a very interesting picture of the upcoming AMD Carrizo mobile APU.
Image credit: SiSoftware
Announced as strictly mobile parts, Carrizo is based on the next generation Excavator core and features what AMD is calling one of their biggest ever jumps in efficiency. Now alleged leaked benchmarks are showing significant performance gains as well, with numbers that should elevate the IGP dominance of AMD's APUs.
Image credit: WCCFtech
"The A10 7850K scores around 270 Mpix/s while Intel’s HD5200 Iris Pro scores a more modest 200 Mpix/s. Carriso scores here over 600 Mpix/s which suggests that Carrizo is more than twice as fast as Kaveri and three times faster than Iris Pro. To put this into perspective this is what an R7 265 graphics card scores, a card that offers the same graphics performance inside the Playstation 4."
While the idea of desktop APUs with greatly improved graphics and higher efficency is tantalizing, AMD has made it clear that these will be mobile-only parts at launch. When asked by Anandtech, AMD had this to say about the possibility of a desktop variant:
“With regards to your specific question, we expect Carrizo will be seen in BGA form factor desktops designs from our OEM partners. The Carrizo project was focused on thermally constrained form factors, which is where you'll see the big differences in performance and other experiences that consumers value.”
The new mobile APU will be manufactured with the same 28nm process as Kaveri, with power consumption up to 35W for the Carrizo down to a maximum of 15W for the ultra-mobile Carrizo-L parts.